News & Events

2019 SVIEF-STAR Spring Demoday

SANTA CLARA, Calif. — Mar. 31, 2019  

  DinoPlusAI was chosen from 200+ Silicon Valley startups to participate 2019 China (Shenzhen) Innovation & Entrepreneurship International Competition (Silicon Valley Division), hosted by SVIEF (Silicon Valley Innovation Entrepreneurship Forum) on March 31, 2019 in Santa Clara, California.  Among 20 teams, DinoPlusAI was awarded the 3rd place.  SVIEF 

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DinoplusAI Partners with SiFive to Develop Mission-Critical AI Processor Platform for High Performance Processing with Ultra-Low Latency


  • Optimized for data centers, 5G/edge cloud and autonomous vehicles
  • Includes SiFive RISC-V E34 Management Core and proprietary DinoplusAI engine, and will be realized into working silicon by SiFive’s Custom SoC Division using robust ASIC design and manufacturing methodology

SAN MATEO, Calif. — Feb. 25, 2019 — SiFive, the leading provider of commercial RISC-V processor core IP, design platforms and silicon solutions, today announced that it was selected by DinoplusAI, an innovator in AI processors and software for high performance mission-critical applications, to develop its mission-critical AI processor platform, which is optimized for ultra-low latency applications, such as data centers, 5G/edge cloud and autonomous vehicles. The DinoplusAI processor platform combines the SiFive RISC-V E34 Management Core with the proprietary AI engine from DinoplusAI. In addition, SiFive’s Custom SoC Division will provide industry-proven robust RTL-to-physical design custom SoC implementation methodology to ensure first-time working silicon and enable high-volume production.

The DinoplusAI processor platform provides consistent ultra-low latency, thus mitigating the common constraints of high-performance AI processing. The DinoplusAI processor features a scalable architecture, software stack and user interfaces. It not only addresses the computing power and energy efficiency required in AI applications, but also the latency, security and reliability that designers of AI products and services rely on. The processor platform is highly consistent and predictable, and has achieved the industry’s lowest latency at low batch size, which is critical in AI applications.  

“We chose to partner with SiFive because of the company’s leadership in RISC-V cores, and its proven success in ASIC design and manufacturing of fully optimized SoCs,” said Jay Hu, CEO of DinoplusAI. “This expertise, combined with our IP blocks for AI, will result in a truly unique solution that optimizes inference with a focus on performance, power efficiency, ultra-low latency, assured security and reliability.”

“The DinoplusAI processor, with superior DeepBench LSTM performance, enables more than 4000 real-time audio streams with a computation latency of less than 1ms for Rokid’s acoustic model, an industry leading cloud speech recognition algorithm,” said Dr. Yi Rao, director of the R-lab at Rokid.

“Meeting the ultra-low latency challenges of AI applications requires a successful platform approach that comprises of a new class of silicon IPs, cores and advanced physical implementation techniques,” said Naveed Sherwani, CEO of SiFive. “The DinoplusAI processor platform features powerful IP, specifically designed by DinoplusAI for next-generation AI applications. We will integrate these AI IP blocks into our 16nm FinFET design platform based on the SiFive RISC-V E34 management core to deliver a complete silicon solution.”

About DinoplusAI

DinoplusAI designs and produces AI processors and software for data centers, 5G/edge cloud computing, autonomous driving and other mission-critical applications. The company’s unique approach optimizes performance, power efficiency and ease of use, while also enabling cost-effective training. DinoplusAI was founded in 2017 and is headquartered in Fremont, CA. For more information, visit http://dinoplus.ai/.

About SiFive

SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. Located in Silicon Valley, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, visit www.sifive.com.