News & Blogs
CEO Jay Hu Presented The Platform for the Future Computing @ SVIEF Conference (Aug 7th, 2019). Jay shared his vision of
- Advancement of communication and computation technology feed each other, to power future computing and new applications.
- 5G powered edge computing and new breed of virtual processing units that offload management functions from CPU with domain specific acceleration will change the communication and computation paradigm, with multiple magnitude improvement on performance and latency.
Mr. Patrick Ang Joins DinoPlusAI August 27, 2019
DinoPlusAI Inc. today is excited to announce that Mr. Patrick Ang has joined full time and will serve as VP of business development.
Patrick is a a serial entrepreneur and seasoned executive in the semiconductor industry. He has over 30 years semiconductor experience in both startup and large corporations. Patrick has raised over $30M in previous funding rounds, co-founded four startups all with successful exit. He has held senior management roles in public listed companies including EVP at OPTi, VP at Creative Technology and COO at ESS Technology.seasoned. Please see the news release for more details.
Dr. Sam Heidari Joins DinoPlusAI August 2, 2019
DinoPlusAI Inc. today is excited to announce that Dr. Sam Heidari has joined its Board of Directors and will serve as the Executive Chairman.
Dr. Heidari is a seasoned technology executive. Recently, he was the Chairman of the board and CEO of Quantenna Communications in which he drove the organization in developing the most advanced Wi-Fi hardware and software solutions to date. Dr. Heidari led Quantenna's successful IPO in 2016 and its subsequent acquisition in 2019. Please see the news release for more details.
Latency Optimized AI Processor for the 5G-enabled Network Edge
June 21, 2019, by Dawn Xie & Jay Hu
AI applications require close to real-time responsiveness. 5G-enabled network edge, which resolves both network latency via URLLC and compute latency by using a new breed of latency optimized processors, will power a new generation of latency sensitive applications through the network edge. Welcome to read new white paper on latency optimized AI processor for 5G-enabled network edge.
DinoPlusAI CEO Jay Hu spoke as a panelist in the "Power Efficient IPs for AI" panel in DAC 2019. DAC is the premier conference devoted to the design and automation of electronic systems (EDA), embedded systems and software (ESS), and intellectual property (IP). Hot topics like Near-Memory Computing, CNN, PPA Optimization, scalability/ flexibility/ Efficiency & Security/privacy was discussed. Other members in the panel include Aditya Mukherjee, Steve Brightfield, Mike Li & Chris Shore. The panel was moderated by Richard Nass, and chaired by Farzad Zarrinfar.
DinoPlusAI Announces its Latency Optimized AI Chipset May 16, 2019
DinoPlusAI founder and CEO Jay Hu announced the industry’s first latency optimized AI processor, Trex, during the Alchemist Accelerator Demo Day on May 16, 2019 in Menlo Park, CA. This AI processor is designed ground up to significantly reduce AI inferencing latency for many AI applications, including image recognition, speech recognition and synthesizing. Dr. Yi Rao from Rokid, a firm specialized in speech recognition using machine learning, also expressed excitement of the performance that DinoPlusAI chipsets provide in the video.
DinoPlusAI won 3rd place in International Competition March 31, 2019
DinoPlusAI was chosen from 200+ Silicon Valley startups to participate in 2019 China (Shenzhen) Innovation & Entrepreneurship International Competition (Silicon Valley Division), hosted by SVIEF (Silicon Valley Innovation Entrepreneurship Forum) on March 31, 2019 in Santa Clara, California. Among the 20 participating teams, DinoPlusAI was awarded the 3rd place. See here for CEO Jay Hu's Presentation.
DinoPlusAI Announces Partnership with SiFive Feb 25, 2019
DinoPlusAI, an innovator in AI processors and software for high performance mission-critical applications, announces to partner with SiFive, the leading provider of commercial RISC-V processor core IP, design platforms and silicon solutions, to develop its mission-critical AI processor platform, which is optimized for ultra-low latency applications, such as data centers, 5G/edge cloud and autonomous vehicles. View here for more details.